volume55-number1 - Flipbook - Page 7
The sub-octave IBW receiver of today, notionally shown by the Figure 2 dashed
box, worries only about IMD3 because it falls in-band and cannot be filtered.
It doesn’t worry much about IP2 because of the easily filtered location of IMD2
and the inducing signals. F3 is easily chopped down using input RF filtering,
which takes F3 – F1 and F3 – F2 way below the noise floor. Much like the F1 and
F2 second harmonics, the F1 + F2 IMD2 is easily attenuated using output filtering.
Of course, the second-order performance of the ADC must be considered in
relation to Nyquist folding spurs, but the front-end IMD2 performance is easy to
deal with.
For the previous SFDR example scenario, the RF front end feeds the ADC with
–20 dBm and has an OIP3 of 20 dBm. The required OIP2 to get the same level
IMD2 and IMD3 spurs, and thereby not limit performance, is:
OIP2 dBm = 2(20 dBm) – (–20 dBm) = 60 dBm
That raw device OIP2 performance is not available today given the balance with
other attributes like frequency, bandwidth, noise, and dc power. This explains
the increasing interest in next-generation adaptive front-end interferer mitigation techniques.
To mitigate IMD2, the receiver must lower the max input operating level from
–20 dBm to –32 dBm, and is then able to achieve an improved SFDR2 of 66 dB
best case. In Figure 3, this optimal SFDR2 is where the IMD2 trace intersects the
noise floor. Alas, the best case SFDR2 at Pin = –32 dBm is still 13 dB worse than
the best case SFDR3 at –20 dBm. Since we’ve now shifted the max operating
level down, this puts the spotlight on noise power (sensitivity) limitations, as
discussed in the next sections.
Enter the multi-octave IBW receiver, notionally shown by the Figure 2 solid box,
and the situation turns on its head. IMD2 is the bigger concern vs. IMD3. The
IMD2 spurs and inducing interferers are now in-band. Band-pass filtering them
defeats the purpose of a multi-octave IBW. This is why tunable notch filtering,
despite its limitations, is seeing increased attention as a front-end interference
mitigator. It doesn’t lop off giant pieces of the multi-octave spectrum.
Figure 3 illustrates the relationship between the fundamental multi-tone large
signal, IMD2 and IMD3 level, noise floor, and the resulting SFDR for an example
multi-octave wideband digital receiver. The example uses real noise and linearity attributes for an ADC sampling the first Nyquist zone with a 4 GHz IBW from
2 GHz to 6 GHz. A processing bandwidth of 469 kHz is assumed.
What Sets Processing Bandwidth in the
Wideband Digital Receiver?
The sensitivity, or noise power, of the EW receiver gets better as the processing
bandwidth narrows. In typical fashion, however, there are trade-offs to balance:
we can’t just reduce the bandwidth to an arbitrarily small value and head to lunch.
What are the competing factors to consider? To answer the question, we need to
discuss decimation, the fast Fourier transform (FFT), and their relationship. First,
we define a couple variables:
Optimal SFDR2 and SFDR3 occur at different Pin operating points where the
respective IMD level intersects the noise power. If we pretend for a moment that
this is a sub-octave receiver with front-end RF band-limiting, SFDR3 sets the
overall SFDR, and we can expect a best case SFDR of 79 dB, which is very good.
But since the EW receiver requires multi-octave IBW, SFDR2 sets the overall
SFDR. At the best SFDR3 input level (Pin = –20 dBm), the IMD2 spurs degrade the
SFDR by 24 dB, resulting in an SFDR of 55 dB. Fair, albeit disappointing, results.
M is the ADC decimation factor of the digital
data stream
ADI’s high sample rate ADCs employ on-chip digital signal processor (DSP) blocks
that allow configurable filtering and decimation of the raw data stream to a
minimum viable payload sent to the downstream FPGA. This process is discussed
in detail across ADI literature.3 The obvious benefit of decimation is reducing the
digital payload that must pass over JESD204B/JESD204C to the FPGA. Another
benefit is the power consumption savings realized using local on-chip decimation-specific circuitry (that is, ASIC) vs. implementing the same operation in
the FPGA fabric. But local on-chip decimation is beneficial beyond just thinning
the data stream and saving power. We’ll get to that.
(3)
In other words, this condition will make the SFDR2 and SFDR3 lines intersect the
noise floor at the same spot, so that SFDR2 is not limiting performance.
Fundamental, IMD2, IMD3, PN, SFDR
20
Fund dBm
IMD2 dBm
IMD3 dBm
PN dBm
0
–20
SFDR3
POUT (dBm)
–40
–60
SFDR2
–80
–100
–120
–140
–160
–160
(5)
N is the FFT length, proportional to the sample
time duration
A useful rule of thumb is that for a specific RF output level = PRF,O to achieve
equivalent IMD2 and IMD3 levels:
OIP2 dBm = 2OIP3 dBm– PRF,O dBm
(4)
–140
–120
–100
–80
–60
Pin (dBm)
–40
–20
0
20
Parameter
Value
Units
fs
15.36
GSPS
IIP3
20
dBm
IIP2
35
dBm
Full scale
–6.5
dBm
NSD
–148
dBFS/Hz
BW_proc
469
kHz
PN
–98
dBm
iSFDR3
79
dB
iSFDR2
66
dB
Figure 3. SFDR2 and SFDR3 tell you how far down from the largest signal (fundamental) you can easily detect a smaller signal. Because it varies widely, the detection threshold is zero here.
In practice, subtract your detection threshold from SFDR.
Analog Dialogue Volume 55, Number 1
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